The need to read and write simultaneously to a computer memory device is satisfied by dual-port memory devices, but dual-port memory devices are relatively expensive compared to single-port memory devices. A single-port memory device, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), can either read or write during any specific time period (typically a single clock cycle), but not both. Methods for simulating a dual-port device using one or more single-port memory devices are well known in the art.
Cypress Semiconductor Corporation, of San Jose, Calif., publish a technical article entitled "Understanding Specialty Memories: Dual-Port RAM," which can be found at:
http://www.cypress.com/design/techarticles/v2n2.html, PA1 which is incorporated herein by reference, explaining how a dual-port device can be simulated by using a multiplexer between two access processes addressing a single-port device. PA1 a single-port random-access memory (RAM) device; and PA1 a first-in first-out (FIFO) buffer, such that when the output word is to be read from the same memory unit to which the input word is to be written in a given clock cycle, one of the input and output words is passed between the respective port of the memory bank and the FIFO buffer, instead of between the respective port of the memory and the RAM device. PA1 providing a plurality of memory units each including a single-port random-access memory (RAM) device and a first-in first-out (FIFO) buffer coupled to the RAM device; PA1 driving the plurality of memory units with a clock producing a sequence of clock cycles; PA1 reading a read word from one of the memory units on each of the clock cycles; and PA1 writing a write word to one of the memory units on each of the clock cycles, such that when the reading and writing occur to the same memory unit on a common one of the clock cycles, one of the read and write words is passed through the FIFO buffer of the memory unit rather than directly to or from the RAM device of the unit.
U.S. Pat. No. 5,818,751 to Ho et al., which is incorporated herein by reference, describes a single-port SRAM with no read/write collisions. The invention uses separate read and write cycles from a clock.
U.S. Pat. No. 5,371,877 to Drako et al., which is incorporated herein by reference, describes a circuit for providing the function of a dual port first-in first-out (FIFO) memory stack. The circuit includes a first and second bank of single port RAMs to which data are written in alternation, and wherein each bank, when not being written to, is read from.
U.S. Pat. No. 5,706,482 to Matsushima et al., which is incorporated herein by reference, describes a method by which a single port memory which is used to store an image can be read from and simultaneously written to. The method uses separate read and write buffers communicating to an arbiter section, which in turn communicates with the single port memory.
U.S. Pat. No. 5,802,579 to Crary, which is incorporated herein by reference, describes a system and method for simultaneously reading and writing data in a single-port random access memory. The system stores new data and a corresponding new data address in a buffer, and compares the new data address with a current read address. In the event that the read and write addresses are the same, the new data are stored at a modified address.